Description of work The project intends to explore the following open scientific questions. -Objective and accurate evaluation of transport properties in advanced devices. – Impact of leakage current on both static and dynamic transistor behaviors resulting from thin (and high-k) gate dielectrics and channel materials with small energy-gap. – Introduction of UTB and UTB2 (with thin buried oxide) device architectures calls for in-depth analysis of substrate bias, optimization of both BOX and film thicknesses, substrate doping. – Reliability tradeoffs associated with new materials /architectural options. – Variability analyses in the extended temperature and frequency ranges.
Requirements The candidate must have obtained a Master degree in electronic engineering, physics, or a related field. Preferably he/she should already have a good background in solid-state physics and be familiar with electrical characterization and TCAD simulations. He/she has to send a CV, a motivation letter, copies of degree certificates, academic record and a letter of recommendation of his/her Master thesis supervisor.
Scholarship Deadline: Contact Employer
Prof. Denis Flandre (denis.flandre-at-uclouvain.be)
Prof. Jean-Pierre Raskin (jean-pierre.raskin-at-uclouvain.be)
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